Pipelining Processor
Pipelining is a technique used in modern processors to improve performance by executing multiple instructions simultaneously. It breaks down the execution of instructions into several stages, where each stage completes a part of the instruction. These stages can overlap, allowing the processor to work on different instructions at various stages of completion.
Design of a basic Pipeline
- In a pipleined processor, a pipeline has two ends, the input and the output end. Between these ends, there are multiple stages/segments such that the output of one stage is connected to the input of the next stage and each stage performs a specific operation.
- Interface registers are used to hold the intermediate output between two stages. These interface registers are also called buffer.
- All the stages in the pipeline along with the interface registers are controlled by a common clock.
Execution in a pipelined processor Execution sequence of instructions in a pipelined processor can be visualized using a space-time diagram. For example, consider a processor having 4 stages and let there be 2 instructions to be executed. We can visualize the execution sequence through the following space-time diagrams:
Non-Overlapped Execution
| Stage / Cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
|---|---|---|---|---|---|---|---|---|
| S1 | I1 | I2 | ||||||
| S2 | I1 | I2 | ||||||
| S3 | I1 | I2 | ||||||
| S4 | I1 | I2 |
Total time = 8 Cycles
Overlapped Execution
| Stage / Cycle | 1 | 2 | 3 | 4 | 5 |
|---|---|---|---|---|---|
| S1 | I1 | I2 | |||
| S2 | I1 | I2 | |||
| S3 | I1 | I2 | |||
| S4 | I1 | I2 |
Total time = 5 Cycles
Pipeline Stages RISC processor has 5 stage instruction pipeline to execute all the instructions in the RISC instruction set. Following are the 5 stages of the RISC pipeline with their respective operations:
- Stage 1 (Instruction Fetch): CPU fetches the instructions from the memory.
- Stage 2 (Instruction Decode): The instruction is decoded and register file is accessed to obtain the value of registers used in the instruction.
- Stage 3 (Instruction Execute): In this stage some of activities are done such as ALU operations.
- Stage 4 (Memory Access): In this stage, memory operands are read and written from/to the memory that is present in the instruction.
- Stage 5 (Write Back): In this stage, computed/fetched value is written back to the register present in the instructions.
Conclusion
Pipelining is one of the most essential concepts and it improes CPU's capability to process several instructions at the same tiem across various stages.